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It is becoming evident that the next level of advancement in chip-building can be achieved through open, modular and collaborative methodologies resulting in unmatched flexibility, ease of development and robustness of the...
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The ASIC design and manufacturing flow has for a long time been dominated by proprietary tools and processes. The growing complexity of chip-building has been reinforcing the claim that “hardware is too hard to be open source...
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Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind. This is unfortunate, as...
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At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools.
Verilog, SystemVerilog and open tooling
