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co-simulation

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OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

CPU RTL CO-SIMULATION IN RENODE

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CPU RTL co-simulation in Renode Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of flexibility and allowing Renode to cover ASIC and FPGA SoC development...
OPEN NETWORKING, OPEN OS, OPEN SOURCE TOOLS

BLUETOOTH MESH NETWORKING PATHFINDING ALGORITHM DEVELOPMENT USING RENODE

Published:

Distributed system map Antmicro’s open source Renode simulation framework offers support for the Bluetooth Low Energy (BLE) protocol and multi-node simulation capabilities, which makes it a great environment for development, debugging and testing...
OPEN NETWORKING, OPEN OS, OPEN SOURCE TOOLS

DEVELOPING AND TESTING BLE PRODUCTS ON NRF52840 IN RENODE AND ZEPHYR

Published:

Arduino Nano 33 BLE Sense board The Bluetooth Low Energy connectivity standard has gained immense popularity in recent years, mainly due to the growing ubiquity of IoT solutions in both consumer electronics and industry. Thanks to its low-power nature, it...
OPEN SOURCE TOOLS, OPEN FPGA

ADVANCED CO-SIMULATION WITH RENODE AND VERILATOR: ZYNQ AND FASTVDMA

Published:

Diagram depicting co-simulation of Zynq Co-simulation is extremely useful for developing complex systems, especially those targeting FPGA SoCs, where specialized IP cores often interact with advanced software running on the hard CPU. Co-simulation has been available...
OPEN SOURCE TOOLS, OPEN NETWORKING

INITIAL BLUETOOTH SUPPORT FOR NRF52840 IN RENODE

Published:

Nordic chips communicating in Renode For several years now we have been working with the Google TensorFlow Lite Micro team on making their ML framework aimed at MCUs and other low-power devices easier to test and demonstrate using our open source simulation framework...
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