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The open source Bazel build system provides hermetic build environments, facilitating reproducible, controllable builds, with local and distributed cache. This approach significantly accelerates the build process and provides...
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The Capability Hardware Extension to RISC-V for Internet of Things (CHERIoT) project provides a hardware platform built around a modified RISC-V Ibex core, designed for enhanced security through limited access of executed applications...
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In a long-running collaboration with Google, Antmicro has been working on demonstrating how the XLS Mid-Level Synthesis toolchain can be used to increase productivity of developing highly parallel ASIC solutions.
The initial...
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A few years back Antmicro introduced the first DDR5 capable platform to our open source FPGA-based Rowhammer research framework developed in cooperation with Google - the Data Center RDIMM DDR5 Tester. The follow-on SO-DIMM...
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The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger systems, standalone embedded MCUs and even many-core server AI processing solutions
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The OpenROAD project provides an open source ASIC toolchain that reduces the entry barriers to the field of hardware development and allows fast-turnaround feedback about your design, helping increase productivity of silicon...
