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Co-simulating HDL has been possible in Renode since the 1.7.1 release, but the functionality - critical for hardware/software co-development as well as FPGA use cases - is constantly evolving based on the needs of our customers...
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Antmicro was founded on the belief that open source can dramatically accelerate technological progress by enabling collaboration, transparency and freedom to customize, improve and combine various solutions, unlocking system...
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We are excited to announce the ARVSOM - Antmicro’s fully open source, RISC-V-based system-on-module featuring the StarFive 71x0 SoC. Using the RISC-V architecture, which Antmicro has been heavily involved in since the early...
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We are happy to announce our involvement in ‘Very Efficient Deep Learning in IoT’ (VEDLIoT) - a project funded by the European Commission and coordinated by Bielefeld University’s CoR-Lab, launched at the end of 2020. Comprising...
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Throughout 2020 we have been hard at work developing proper, portable SystemVerilog support for multiple open-source FPGA and ASIC design tools used by us and our customers, most notably Yosys and Verilator. We strongly believe...
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For over a year now we have been working together with QuickLogic towards supporting their FPGA devices in open source FPGA tooling. This is the first time in history where an FPGA vendor has gotten directly involved in enabling...
