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verification

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

ADDING PHYSICAL MEMORY PROTECTION TO THE VEER EL2 RISC-V CORE

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PMP for VeeR EL2 - graphical interpretation Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality checks, code...
OPEN SOURCE TOOLS, OPEN HARDWARE, OPEN SIMULATION

HIGH-FREQUENCY HARDWARE DESIGN WITH OPEN SOURCE SIGNAL INTEGRITY ANALYSIS

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VSD block diagram of the data processing flow Hardware design of advanced video processing devices is one of the key areas of activity at Antmicro. With a never-ending pursuit of higher data throughput, signal integrity moves to the forefront of challenges in modern PCB...
OPEN SOURCE TOOLS, OPEN ASICS

INITIAL OPEN SOURCE SUPPORT FOR UVM TESTBENCHES IN VERILATOR

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Running simple UVM testbenches in Verilator Leading the efforts of the Tools Workgroup in CHIPS Alliance, across a variety of customer projects, as well as own R&D, at Antmicro we are actively looking for and capturing the productivity enhancements that can be achieved...
OPEN SOURCE TOOLS, OPEN ASICS

PROGRESS IN OPEN SOURCE SYSTEMVERILOG / UVM SUPPORT IN VERILATOR

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Verilator and UVM illustration Verilator is a shining example of a widely-accepted open source tool which provides state-of-the-art results in the ASIC design space. It is commonly used for simulation and testing, but originally, due to the lack of capability...
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