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Verilator is a shining example of a widely-accepted open source tool which provides state-of-the-art results in the ASIC design space. It is commonly used for simulation and testing, but originally, due to the lack of capability...
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As part of the effort to introduce open source tools and building blocks to ASIC development, together with other CHIPS Alliance members, Antmicro has been supporting the Multi-Project-Wafer (MPW) shuttle program, using the...
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Verilator is a fast, open source simulator widely used in the ASIC and FPGA ecosystem, offering state-of-the-art (or better) results in contexts otherwise dominated by proprietary offerings. Its open source nature and the promise...
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At Antmicro we strongly believe that open source flows are key to bringing software-driven innovation into the ASIC space, in order to build a collaborative ecosystem and scalable, reproducible and publicly available components...
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Verilator is a popular open source SystemVerilog simulator and one of the key tools in the ASIC and FPGA ecosystem, which Antmicro is actively using and developing, e.g. by enabling co-simulation with Renode or Cocotb integration
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The growing cost and complexity of advanced nodes, supply chain issues and demand for silicon independence mean that the ASIC design process is in need of innovation. Antmicro believes the answer to those challenges is bound...
