Open Source Silicon w/ RISC-V at TU Munich, Germany


RISC-V logo

Following the recent announcement of RISC-V as Analyst’s Choice: Technology of the Year 2016, and reflecting the growing interest around it in Europe, knowledge-seekers and representatives of businesses in and around Bavaria drew to the Free and Open Source Silicon (FOSSi) Foundation’s “Open Source Silicon with RISC-V” event to learn more about the idea behind an open and license-free ISA and its implications.

Held on March 23rd, 2017 in Munich (courtesy of TU Munich), the meeting co-organized by the FOSSi and the RISC-V Foundation welcomed three entry-level lectures: one by Stefan Wallentowitz of FOSSi about their goals and our common interest in advancing open solutions as global standards, the second by Krste Asanović of Si-Five on the case for RISC-V and the governance of the Foundation (“Instruction Sets Want to be Free!”), and the third by Rob Mullins of lowRISC presenting further plans for their Linux-capable 64-bit SoC.
The talks altogether constituted a good overview of how RISC-V and open source silicon are transforming the computing industry, why everyone that has somehow missed this should get involved and what to expect in the nearest future (one hint - a lot of great stuff).

FOSSi Munich 2017

Among various announcements (e.g. about the co-location of this year’s ORCONF with the excellent Wuthering Bytes festival in the UK) the most important was probably next week’s release of the RISC-V edition of Dave Patterson and John Henessy’s iconic Computer Organization & Design.

The importance of this event is unprecedented - a new generation of electrical engineers and computer scientists will be soon be learning about RISC-V, but unlike with other proprietary architectures, they can actually go on and implement or contribute to open source implementations of the ISA, without needing anyone’s license or permission.

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Coming back to the event itself, it gathered an audience of several dozen participants, including representatives of about 30 companies interested to gain a better understanding of the RISC-V paradigm. The interest was best reflected in the Q&A sessions that followed the talks, and the discussions continued late into the night with drinks and refreshments sponsored by the RISC-V Foundation.

FOSSi Munich 2017

During the evening, ideas and plans for the future were shared between the overlapping communities of RISC-V and FOSSi. Antmicro presented the working prototype of our RISC-V SoM and baseboard (featuring SiFive’s FE310 chip) which is meant as an enabler to carry the hardware implementation into the hands of community influencers, and the group talked about how the joint efforts can be better synchronized to carry forward the ideas of the open ISA and open silicon in general.

The Birds of a Feather sessions that followed the next day were also highly successful, and low-volume (and less overhead) manufacturing, software support, licensing and other important subjects were discussed between the representatives of lowRISC, SiFive, ETH Zurich, Antmicro, Xilinx, Imec and others.

The event was highly enjoyable and fruitful, and there are plans to organise similar gatherings targeted at local communities interested in FOSSi and RISC-V in the future.