Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode
Topics: Open ASICs, Open tools, Open security/safety
An interesting article was published yesterday by All About Circuits on “Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode”. In collaboration with our fellow RISC-V Foundation member, partner and customer Dover Microsystems, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.
The article discusses a real-life customer case that serves as an example of how Renode users are able to leverage the tool to drastically reduce the length of their design cycles, provide a simple and effective means for customers to evaluate their solutions, and to begin adapting software collateral in parallel with hardware integration efforts.
“The Renode framework’s flexible nature, its open-source availability, and the existence of commercial support provided by its authors made it easy for Dover to first build a prototype implementation of their desired workflow and then contract Antmicro to implement (and release into the open-source domain) functionalities that made Renode even better suited for their use case, such as per-instruction execution”, Dover’s Greg Sullivan reveals.
To learn more about how Renode can streamline co-design projects, visit renode.io. To learn more about how CoreGuard can protect embedded systems from network-based attacks, request a demo to see CoreGuard in action.