Renode 1.7 with new soft platforms and TSN/PTP support released
Topics: Open source tools, Open networking, Open FPGA
Antmicro has recently released Renode 1.7 and 1.7.1, one of the largest updates yet of the open source multi-node simulation framework that has been gaining popularity and showcasing new market implementations in the RISC-V ecosystem. With a range of important new platforms (primarily FPGA softcores) and introducing experimental support for Time-Sensitive Networking (TSN) and Precision Time Protocol (PTP) for ARM and RISC-V platforms, as well as numerous fixes and general improvements, Renode now offers even more flexibility and scalability in a unique software/hardware co-development design cycle.
New platforms (soft RISC-V and more)
First of all, we have added support for PicoRV32, a size-optimized RISC-V soft CPU. It is interesting to note that in order to introduce PicoRV32, support for custom instructions in RISC-V needed to be added to Renode. Thus, starting with this release, Renode will allow you to easily customize the RISC-V instruction set - a nice demonstration of Renode’s modularity and extendibility.
Support for PicoRV32, in addition to the award-winning VexRiscv FPGA implementation of RISC-V that we’ve enabled in Renode previously, is now also available as a choice for the configurable LiteX SoC. LiteX support in Renode has been further upgraded with timer and Ethernet (LiteEth) peripheral models.
A complete platform from the author of VexRiscv, the lightweight Murax SoC written in Spinal HDL (and targeting platforms as small as the Lattice iCE40), has also been added, with UART, timer and GPIO controller models to help you start developing right away.
Outside the soft platform topic and on the ARM side, you can now start prototyping on Microchip’s SAM E70 Xplained with Cortex-M7 thanks to USART, TRNG and Ethernet controller models that were added, furthering the portfolio of Microchip platforms supported in Renode.
TSN/PTP and Automatic Network Testing
One of the major updated within release 1.7 is adding initial support for Time-Sensitive Networking (TSN) and Precision Time Protocol (PTP). TSN/PTP capabilities were added to the popular Cadence GEM Ethernet controller that had already been included in the framework, and we will be looking to expand this in the future to address developer needs for specific use cases. The work so far was performed related to our TSN/PTP implementation in Zephyr for the Microchip SAM E70, and having the ability to perform Continuous Integration of that subsystem in Renode is very useful for making sure that other changes in the networking stack of the Zephyr RTOS does not introuce any regressions. Also, to enable easier testing of similar scenarios in the future, a network interface tester for Robot tests is now available.
Further fixes and improvements in Renode 1.7.1 + Verilator integration
Release 1.7 introduces several fixes in previous platform models, as well as visibly improved execution determinism and general usability. A follow-up release (Renode 1.7.1) has been published since with an added integration layer for Verilator. This means you can take your hardware implementations written in Verilog and use them (via Verilator) within a Renode simulation. The release also includes a demo with a ‘verilated’ UARTLite model connected to a RISC-V platform via the AXI4-Lite bus running Zephyr; and a Linux-based example for LiteX with VexRiscv.
Renode presented at SiFive tech Symposiums and at the RISC-V Zurich workshop
Related to all the new developments, Renode is touring the world to showcase some of the exciting news and use cases. Following Antmicro’s participation in the Getting Started with RISC-V North America Roadshow, the proceedings for which are now available, a well-received presentation which sparked lots of interesting discussions was given at last week’s SiFive Tech Sympostium in Stockholm, to be repeated this Thursday at the event’s Munich counterpart. Antmicro collaborates with SiFive to facilitate the adoption of RISC-V among its customers through prototyping, software and simulation services using Renode.
If you weren’t able to plan for either of the SiFive seminars, or the already sold out RISC-V Zurich workshop of which we are a sponsor, reach out to us at firstname.lastname@example.org and we will gladly help you in adopting a software-driven development methodology with Renode.