OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

SYSTEMC CO-SIMULATION IN RENODE

Published:

SystemC co-simulation in Renode, hero image

SystemC is a C++-based system design and verification language and library that allows for modeling of hardware systems, widely used by IP vendors who often provide SystemC-based models for their blocks. Based on community demand, recently we have extended...

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

INITIAL ASSERTION CONTROL SUPPORT IN VERILATOR

Published:

Initial assertion control support in Verilator

Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending Verilator with new verification...

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