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The Xtensa architecture, originally from Tensilica (now part of Cadence), is the base for a family of licensable, configurable cores, enabling easy customization.
This is especially useful in certain applications such as DSP (digital signal processing...
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At Antmicro we work with a large variety of FPGA chips, starting from very large FPGAs we’re using for prototyping ASIC systems, to super small, resource constrained devices to be deployed at the very edge.
One of such devices is the tiny and open source...
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Many years ago, we created an open source tool to assist us in developing new and exciting hardware-accelerated devices with the Zynq 7000 SoC family. The SoC was a novelty at that time, featuring a dual-core ARM Cortex-A9 CPU and a scalable amount of FPGA...
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Verilator is a popular open source SystemVerilog simulator and one of the key tools in the ASIC and FPGA ecosystem, which Antmicro is actively using and developing, e.g. by enabling co-simulation with Renode or Cocotb integration. It’s also one of the fastest...
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Our work together with Google and the world’s research community on detecting and mitigating the Rowhammer problem in DRAM memories has been proving that the challenge is far from being solved and a lot of systems are still vulnerable.
The DDR Rowhammer...
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The growing cost and complexity of advanced nodes, supply chain issues and demand for silicon independence mean that the ASIC design process is in need of innovation. Antmicro believes the answer to those challenges is bound to come from the software-driven...
