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simulation

OPEN NETWORKING, OPEN SOURCE TOOLS

SIMULATING NB-IOT NETWORKING IN RENODE

Published:

Simulating NB-IoT networking in Renode Repeatable testing and debugging are notoriously difficult in IoT system development, as they typically involve multiple devices connected by different networks, making it hard to pinpoint the exact root of a problem and reliably...
OPEN SOURCE TOOLS, OPEN NETWORKING

PRE-SILICON SECURE ASIC DEVELOPMENT BASED ON OPENTITAN IN RENODE

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OpenTitan Renode platform OpenTitan is a community-driven open source Root of Trust project that provides secure, tested, and transparent building blocks and infrastructure for designing and implementing trusted computing systems. On the basic level...
OPEN OS, OPEN SOURCE TOOLS

TESTING ZEPHYR SOFTWARE USING NEW CMOCK/UNITY MODULE AND RENODE

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Testing Zephyr software using CMock/Unity Proper testing of embedded software is very difficult, but also crucial to successful product development. In Antmicro’s work, testing has always played a pivotal role - the open source Renode simulation framework that we maintain...
OPEN SOURCE TOOLS, OPEN MACHINE VISION

GITHUB ACTION FOR V4L2 APPLICATION TESTING IN RENODE

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GitHub action for v4l2 application testing illustration Antmicro’s work with camera systems often results in new reusable tools and libraries helpful for debugging video devices and applications. Some examples of such tools for working with v4l2 pipelines such as grabthecam, farshow
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

CPU RTL CO-SIMULATION IN RENODE

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CPU RTL co-simulation in Renode Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of flexibility and allowing Renode to cover ASIC and FPGA SoC development...
OPEN SOURCE TOOLS, OPEN ASICS

PROGRESS IN OPEN SOURCE SYSTEMVERILOG / UVM SUPPORT IN VERILATOR

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Verilator and UVM illustration Verilator is a shining example of a widely-accepted open source tool which provides state-of-the-art results in the ASIC design space. It is commonly used for simulation and testing, but originally, due to the lack of capability...
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