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Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind. This is unfortunate, as...
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RISC-V Foundation Platinum Founding Member Antmicro will be exhibiting at RISC-V Summit 2019, the annual global conference for the disruptive open ISA that is paving the way for open digital design. The show will be hosted...
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At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools.
Verilog, SystemVerilog and open tooling
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Antmicro’s dedication to supporting the ongoing paradigm shift of computer engineering towards open chip design is reconfirmed by the company’s recent upgrade of its membership status in CHIPS Alliance to Gold.
Following...
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The inaugural CHIPS Alliance Workshop, due to start tomorrow, June 19th, 2019 at Google’s Sunnyvale campus, CA, will see member companies Antmicro, Esperanto, Google, SiFive and Western Digital welcoming industry stakeholders...
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Cocotb
One of the great open source tools in our arsenal that we’ve grown very fond of throughout the years is Cocotb, a very clever framework for simulating HDL (VHDL, Verilog or SystemVerilog) designs. Cocotb is maintained...
